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XC9500XL High-Performance CPLD Family
Description:
The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for
high-performance, low-voltage applications in leading-edge
communications and computing systems, where high device reliability
and low power dissipation is important. Each XC9500XL device
supports in-system programming (ISP) and the full IEEE Std 1149.1
(JTAG) boundary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL family is
designed to work closely with the Xilinx® Virtex®, Spartan®-XL and
XC4000XL FPGA families, allowing system designers to partition
logic optimally between fast interface circuitry and high-density
general purpose logic. As shown in Table 1, logic density of the
XC9500XL devices ranges from 800 to 6400 usable gates with 36 to
288 registers, respectively. Multiple package options and
associated I/O capacity are shown in Table 2. The XC9500XL family
members are fully pin-compatible, allowing easy design migration
across multiple density options in a given package footprint.
The XC9500XL architectural features address the requirements of
in-system programmability. Enhanced pin-locking capability avoids
costly board rework. In-system programming throughout the full
commercial operating range and a high programming endurance rating
provide worry-free reconfigurations of system field upgrades.
Extended data retention supports longer and more reliable system
operating life.
Advanced system features include output slew rate control and
user-programmable ground pins to help reduce system noise. Each
user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the
outputs may be configured for 3.3V or 2.5V operation. The XC9500XL
device exhibits symmetric full 3.3V output voltage swing to allow
balanced rise and fall Times .
Applications:
• Optimized for high-performance 3.3V systems
- 5 ns pin-to-pin logic delays, with internal system frequency up
to 208 MHz
- Small footprint packages including VQFPs, TQFPs and CSPs (Chip
Scale Package)
- Pb-free available for all packages
- Lower power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS FastFLASH technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with FastCONNECT II switch
matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term
allocation
- Local clock inversion with three global and one product-term
clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Supports hot-plugging capability
- Full IEEE Std 1149.1 boundary-scan (JTAG) support on all devices
• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable gates
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention
• Pin-compatible with 5V core XC9500 family in common package
footprints
Specifications:
Datasheets | XC9536XL |
Product Photos | XC9536XL-10VQG44C |
Standard Package | 160 |
Category | Integrated Circuits (ICs) |
Family | Embedded - CPLDs (Complex Programmable Logic Devices) |
Series | XC9500XL |
Packaging | Tray |
Programmable Type | In System Programmable (min 10K program/erase cycles) |
Delay Time tpd(1) Max | 10.0ns |
Voltage Supply - Internal | 3 V ~ 3.6 V |
Number of Logic Elements/Blocks | 2 |
Number of Macrocells | 36 |
Number of Gates | 800 |
Number of I /O | 34 |
Operating Temperature | 0°C ~ 70°C |
Mounting Type | Surface Mount |
Package / Case | 44-TQFP |
Supplier Device Package | 44-VQFP (10x10) |
Other Names | 122-1385 |
Competitive Advantage:
Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .
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