XC5VLX110-1FFG676C 4608kbit 440 I/O Virtex 5 FPGA
Brand Name:Xilinx Inc.
Certification:Lead free / RoHS Compliant
Model Number:XC5VLX110-1FFG676C
Minimum Order Quantity:1 pcs
Delivery Time:3-5 Day
Payment Terms:T/T, Western Union, Paypal, Trade Assurance, Credit Card
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Product Details
XC5VLX110-1FFG676C Xilinx FPGA Chip FBGA-676 440 I/O Virtex-5
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| FPGA - Field Programmable Gate Array | |
| Virtex-5 | |
| 440 I/O | |
| 1 V | |
| 0 C | |
| + 85 C | |
| SMD/SMT | |
| FBGA-676 | |
| Series: | XC5VLX110 |
| Brand: | Xilinx |
| Distributed RAM: | 1120 kbit |
| Embedded Block RAM - EBR: | 4608 kbit |
| Maximum Operating Frequency: | 550 MHz |
| Moisture Sensitive: | Yes |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
Summary of Virtex-5 FPGA Features
• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• 25 x 18 two’s complement multiplication
• Optional pipeline stages for enhanced performance
• Optional 48-bit accumulator for multiply accumulate (MACC) operation with optional accumulator cascade to 96-bits
• Integrated adder for complex-multiply or multiply-add operation
• Optional bitwise logical operation modes
• Independent C registers per slice
• Fully cascadable in a DSP column without external routing resources
• On-Chip temperature measurement (±4°C)
• On-Chip power supply measurement (±1%)
• Easy to use, self-contained
− No design required for basic operation
− Autonomous monitoring of all on-chip sensors
− User programmable alarm thresholds for on-chip
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• 25 x 18 two’s complement multiplication
• Optional pipeline stages for enhanced performance
• Optional 48-bit accumulator for multiply accumulate (MACC) operation with optional accumulator cascade to 96-bits
• Integrated adder for complex-multiply or multiply-add operation
• Optional bitwise logical operation modes
• Independent C registers per slice
• Fully cascadable in a DSP column without external routing resources
• On-Chip temperature measurement (±4°C)
• On-Chip power supply measurement (±1%)
• Easy to use, self-contained
− No design required for basic operation
− Autonomous monitoring of all on-chip sensors
− User programmable alarm thresholds for on-chip
XC5VLX110-1FFG676C 4608kbit 440 I/O Virtex 5 FPGA
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