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1.Abstract
The SCALE™-2+ dual-driver core 2SC0435T2G1-17 (Connector pin length of 3.1mm, suitable for PCB thickness of 2mm; increased EMI capability; lead free) / 2SC0435T2G1C-17 (Coated version using ELPEGUARD SL 1307 FLZ/2 from Lackwerke Peters) combines unrivalled compactness with broad applicability. The driver is designed for universal applications requiring high reliability. The 2SC0435T2G1(C)-17 drives all usual high-power IGBT modules up to 1700V. The embedded paralleling capability allows easy inverter design covering higher power ratings. Multi-level topologies are also supported. The 2SC0435T2G1(C)-17 is the most compact driver core in its power range with a footprint of only 57.2 x 51.6mm and an insertion height of max. 20mm. It allows even the most restricted insertion spaces to be efficiently used. Compared with conventional drivers, the highly integrated SCALE-2+ chipset allows about 85% of components to be dispensed with. This advantage is impressively reflected in increased reliability. The 2SC0435T2G1(C)-17 combines a complete two-channel driver core with all components required for driving, such as an isolated DC/DC converter, short-circuit protection, Advanced Active Clamping as well as supply voltage monitoring. Each of the two output channels is electrically isolated from the primary side and the other secondary channel. An output current of 35A and 4W drive power is available per channel, making the 2SC0435T2G1(C)-17 an ideal driver platform for universal usage in medium and high-power applications. The driver provides a gate voltage swing of +15V/-10V. The turn-on voltage is regulated to maintain a stable 15V regardless of the output power level. Its outstanding EMC allows safe and reliable operation in even hard industrial applications.
2.Footnotes to the Key Data
1)The maximum peak gate current refers to the highest current level
occurring during the product lifetime. It is an absolute value and
does also apply for short pulses.
2)The average supply input current is limited for thermal reasons.
Higher values than specified by the absolute maximum rating are
permissible (e.g. during power supply start up) if the average
remains below the given value, provided the average is taken over a
time period which is shorter than the thermal time constants of the
driver in the application.
3)There is no means of actively controlling or limiting the input
current in the driver. In the case of start-up with very high
blocking capacitor values, or in case of short circuit at the
output, the supply input current has to be limited externally.
4)The maximum output power must not be exceeded at any time during
operation. The absolute maximum rating must also be observed for
time periods shorter than the thermal time constants of the driver
in the application.
5)An extended output power range is specified in the output power
section for maximum ambient temperatures of 70°C. In that case, the
absolute maximum rating for the operating temperature changes to
(-40°C - 70°C) and the absolute maximum output power rating changes
to 6W.
6)The delay time is measured between 50% of the input signal and
10% voltage swing of the corresponding output. The delay time is
independent of the output loading.
7)Output rise and fall times are measured between 10% and 90% of
the nominal output swing with an output load of 4.7Ω and 270nF. The
values are given for the driver side of the gate resistors. The
time constant of the output load in conjunction with the present
gate resistors leads to an additional delay at the load side of the
gate resistors.
8)External blocking capacitors are to be placed between VISOx and
VEx as well as VEx and COMx for gate charges exceeding 3μC. Ceramic
capacitors are recommended. A minimum external blocking capacitance
of 3μF is recommended for every 1μC of gate charge beyond 3μC.
Insufficient external blocking can lead to reduced driver
efficiency and thus to thermal overload.
9)The minimum response time given is valid for the circuit given in
the description and application manual (Fig. 7) with the values of
table 1 (Cax = 0pF, Rthx = 43kΩ).
10)The blocking time sets a minimum time span between the end of
any fault state and the start of normal operation (remove fault
from pin SOx). The value of the blocking time can be adjusted at
pin TB. The specified blocking time is valid if TB is connected to
GND. 11)Undervoltage monitoring of the primary-side supply voltage
(VCC to GND). If the voltage drops below this limit, a fault is
transmitted to both SOx outputs and the power semiconductors are
switched off. 12)Undervoltage monitoring of the secondary-side
supply voltage (VISOx to VEx and VEx to COMx which correspond with
the approximate turn-on and turn-off gate-emitter voltages). If the
corresponding voltage drops below this limit, the IGBT is switched
off and a fault is transmitted to the corresponding SOx output.
13)Transmission delay of fault state from the secondary side to the
corresponding primary status output.
14)HiPot testing (= dielectric testing) must generally be
restricted to suitable components. This gate driver is suited for
HiPot testing. Nevertheless, it is strongly recommended to limit
the testing time to 1s slots as stipulated by EN 50178. Excessive
HiPot testing at voltages much higher than 1200VAC(eff)may lead to
insulation degradation. No degradation has been observed over 1min.
testing at 5000VAC(eff). Every production sample shipped to
customers has undergone 100% testing at the given value for 1s.
15)Partial discharge measurement is performed in accordance with
IEC 60270 and isolation coordination specified in EN 50178. The
partial discharge extinction voltage between primary and either
secondary side is coordinated for safe isolation to EN 50178.
16)Jitter measurements are performed with input signals INx
switching between 0V and 5V referred to GND, with a corresponding
rise time and fall time of 15ns.
17)The component surface temperature, which may strongly vary
depending on the operating condition, must be limited to the given
value for coated driver versions to ensure long-term reliability of
the coating material.
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